Interfaces with oxides
Computer chips based on silicon have transformed society over the last fifty years, but new materials are being built into chips all the time to make them smaller and faster. Silicon was chosen as a semiconductor for logic circuits largely because of the quality of the interface to its oxide. Electrical current in fact moves more than twice as fast through germanium than through silicon, but it forms a poor interface to its oxide. In the last few years however, new high-permittivity oxides are being used in transistors, and chip manufacturers are revisiting germanium. What kind of interface would it form with the new oxides?
We have been simulating the structures that will be formed when high-permittivity oxides are interfaced with a germanium semiconductor in the logic element of the chip. The dimensions of these devices will be well below 50 nanometers (you could line up a million of them around the circumference of a human hair) and so the structure of individual atomic layers at this interface will be important for how well the device works.
In recent years, advances in theoretical approaches and computing power have allowed high-level quantum mechanical simulations of ever-increasing complexity: first of pure solids and then of their surfaces. Computing interfaces is the next frontier for materials simulation. Interfaces are in any case of increasing importance for nanotechnology, including the nanoelectronics application outlined above. To cover the ensemble of possible interface structures, we have generated a series of atomic models that span the extremes of what is experimentally-realisable. Simulated annealing and geometry optimisation was carried out on each model to ensure a realistic structure, and the quantum mechanical energy was used to assess relative stability.
The results reveal for the first time the atomic-scale structure of sub-stoichiometric interfacial layers GeOx, and in particular the differences between silicon and germanium. The Ge-Ge dimers that are a feature of the bare surface are also found to play a role in the interface. The simulations show that annealing in oxygen will lead to progressive growth of a germanium sub-oxide interfacial layer, via a cycle of cleavage and formation of dimers. Dimer formation means that defects, such as three-coordinate Ge, occur spontaneously in the interfacial layer, and this will spoil the electrical performance of the nano-device.