Modeling and Simulation of Fractional - N Frequency Synthesizers

Fast behavioral simulation of fractional-N synthesizers is challenging. The synthesizer's high output frequency (often in the gigahertz range) imposes a high simulation sample frequency for simulators. Unfortunately, the overall PLL dynamics have a bandwidth that is typically three to four orders of magnitude lower than the output frequency (often 100 kHz to 1 MHz of bandwidth compared to 1 to 10 GHz for the output frequency). Thus, simulators take a long time to compute the system's transient response because they must process many simulation samples. A Verilog-AMS model of a fractional-N frequency synthesizer is presented that is capable of predicting spurious tones as well as noise and jitter performance. The model is based on a voltage-domain behavioral simulation. Simulation efficiency is improved by merging the voltage controlled oscillator (VCO) and the frequency divider. Due to the benefits of Verilog-AMS, the Delta-Sigma modulator which is incorporated in the synthesizer is modeled in a fully digital way. This makes it accurate enough to evaluate how the performance of the frequency synthesizer is affected by cyclic behavior in the Delta-Sigma modulator.

 

Reference:

Z. Ye, W. Chen and M.P. Kennedy. Modeling and Simulation of DS Fractional-N PLL Frequency Synthesizer in Verilog-AMS, IEICE Trans. of Fundamentals of Electronics, Communications and Computer Sciences, vol. E90A, no. 10, pp. 2141-2147, Oct 2007.

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