| IC system voltages are rapidly dropping while power requirements are steadily increasing resulting in significant increases in the current delivered from the power supply. This trend coupled with the increased switching speeds of power semiconductor devices, and the reduction of R on for MOSFETs, (factor of 10 reduction in 20 years), are testing the performance limits of power packaging. Thus the silicon die-power circuitry interconnect has now become the critical technological barrier to achieving optimum performance. This is due to the limitations of wire bonds in terms of current carrying capability, parasitic inductance and thermal management capability.
The embedded packaging research activity is concerned with the development of two multi-chip packaging technologies capable of embedding standard power die (i.e. greater than 200 m m thick). These packaging technologies are; “Chip in PCB” and “Chip in polymer build-up layer”. Both technologies will replace wire bond connections with plated copper interconnect. The research will include the design and fabrication of a complete power converter using each of the packaging approaches. These converters will be benchmarked directly against the best available commercial converter.
Expected Benefits
- Enhanced reliability and improved performance through the removal of wire-bond and solder interconnections
- Automated batch level processing leading to increased repeatability and reduced costs
- Potential for increased integration and functionality
- Increased power density and miniaturisation
- Potential to use thinned silicon and chip stacking techniques
P ower Packaging Platforms for next generation power supplies - P Cubed
- Funded by Enterprise Ireland under the Industry led research for Power Electronics programme (ILRP/05/PEIG). The project answered a call for proposals based on a research programme devised by the “Power Electronics Industry Group”.
- P Cubed is concerned with developing novel power packaging technologies for “high density power conversion”. Research partners for the project are UCC and CIT. A number of fabrication innovations have been demonstrated in a first “reduction to practice” demonstrator and hence we are presently writing a patent application.
- This 3 year project commenced at the beginning of 2006
Links
Contact: Paul McCloskey – paul.mccloskey@tyndall.ie | webpage
Selected Publications
- Weimin Chen, Paul McCloskey, James F. Rohan, Patrick Byrne, and Patrick J. McNally, Senior Member, IEEE, “ Preparation and Temperature Cycling Reliability of Electroless Ni(P) Under Bump Metallization”, IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES , VOL. 30, NO. 1, MARCH 2007, pages 144- 151
- Chen WM, McCloskey P, O'Mathuna SC, “ Isothermal aging effects on the microstructure and solder bump shear strength of eutectic Sn37Pb and Sn3.5Ag solders”, MICROELECTRONICS RELIABILITY 46 (5-6): 896-904 MAY-JUN 2006.
- W.-M. Chen, P. McCloskey, P. Byrne, P. Cheasty, G. Duffy, J.F. Rohan, J. Boardman , A. Mulcahy, S. C. O'Mathuna , “Degradation of electroless Ni(P) under bump metallization (UBM) in Sn3.5Ag and Sn37Pb solders during high temperature storage ”, J. Electron. Mater ., 33(8): 900-907, 2004.
- Seán Cian Ó Mathúna, Patrick Byrne, Gerald Duffy, Weimin Chen, Matthias Ludwig, Terence O’Donnell, Paul McCloskey, Maeve Duffy (NUI Galway), “ Packaging and Integration Technologies for Future High Frequency Power Supplies” IEEE Transactions on Industrial Electronics, Vol 51, No. 6, December 2004
- M. Tuttle, P. Byrne, N. Cordero, S.C. O’ Mathuna, P. McCloskey, P. Cheasty & D. O’ Sullivan , "Demonstration Of Increased Power Densities Through Advanced 3d Power Packaging", IMAPS Europe, June 2004
- W.-M. Chen, J.F. Rohan, P. J. McNally+, L. O'Reilly +, P.Byrne, P. McCloskey, S.C. O'Mathuna, “Effects of under bump metallization on the Solder bump reliability, IMAPS2004 ( USA). + Microelectronics Group, Research Institute for Networks and Communications Engineering (RINCE), Dublin City University, Dublin 9, Ireland
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