• High density interconnection
• Nanowire- anisotropic conductive film
• Nanotube-nanowire composites

Innovation in assembly and packaging is accelerating in response to the realization that packaging is now the limiting factor in cost and performance for many types of devices. Near term difficult challenges exist in all phases of the assembly and packaging process from design through manufacturing, test and reliability. Many critical technology requirements are yet to be met and meeting these requirements will require significant investment in research and development. According to ITRS roadmap 2005 the challenges in assembly and packaging technology may be summarised as follows:

1. 3D Packaging which includes bumpless interconnect architecture, thermal management, high frequency and high current density issues.
2. Small die with high pad count and high current density packages, which includes Electromigration, thermal/mechanical reliability modelling, whisker growth and thermal dissipation issues.
3. Flexible System Packaging Conformal, which includes low cost interconnection, small and thin die assembly

In order to achieve some of the above-mentioned challenges we focus on the innovative nanowire/nanotube composite to be used as next generation interconnect materials. Two representative SEM images of aligned nanowire-polymer composite and top of nanowires embedded inside alumina is shown below:

SEM image of cross section of nanowire-polymer composite SEM image of top of metal nanowires embedded inside alumina

Relevant Project: E-cubes: 3-D-Integrated Micro/Nano Modules for Easily Adapted Applications (European Union Integrated project)

Flip chip interconnection by traditional solder bumping or Anisotropically Conductive Films (ACF), containing conductive particles with micrometer size will face more and more challenges due to ever decreasing I/O pitch on Si. Tyndall’s contribution in this project will address this challenge using high aspect-ratio nanowires instead of conductive particles for electrical interconnection between the Si chip and substrate. Therefore we intend to study a new type of interconnection layer (chip) technology composed of nanowires embedded in a polymer or dielectric. Unlike some other composed material synthesized by blending nanowires, nanotubes and/or powders in polymer, the proposed arrangement of nanowires in polymer or in dielectric is highly ordered in X, Y, and Z direction and thereby enabling anisotropic conductance.

Contact: Dr. Alan Mathewson – alan.mathewson@tyndall.ie