As the demands for higher wiring connectivity and shorter distances between chips have increased, so has the development of 3D silicon chip stacks, 3D packaging structures and system-on-silicon LSIs. Of the existing 3D package technology options, wire-bonding remains the most popular method for low density connections of less than 200 I/O per chip. In the near future, however, it will become difficult to meet the increasing frequency requirements and demands for wiring connectivity merely by increasing the number of the peripheral wire-bonds. In order to overcome such wiring connectivity issues, 3D chip stacking technology using through silicon vias (TSV) is attractive because it offers the possibility of solving the serious interconnection problems while offering integrated functions for higher performance.

Through silicon via (TSV) technology is one of the critical and enabling technologies for 3D chip stacking. The benefits of 3D architectures with TSV technology for future ICs include reduced interconnect delay due to shorter chip to chip interconnection lengths, smaller die size which is motivated by the portable and hand held applications, and ability to use distinct, even heterogeneous technologies (analog, logic, RF, MEMS, SiGe, III-V) on separate vertically interconnected layers to build complex systems.

At Tyndall, we are capable of fabricating straight and sloped TSV’s with a high aspect ratio using modified DRIE (Deep Reactive Ion Etching) Bosch processes.

The Deep_1 process is an optimized Bosch process to deep etch Si providing a vertical angle, with high SiO2 mask selectivity and high Si etch rate (up to 11um/min). This process works fine for aspect ratios less than 10.

Fig 1. Straight wall TSV’s fabricated at Tyndall

There are a number of recipes available on the STS which are conditioned for slope control in bulk silicon, one of which, a switching recipe of BOSCH and isotropic etching has the ability to provide different degrees of sidewall angle and taper to depths >300um. The Si_Slope recipe, recently developed at Tyndall on the STS-HRM, provides about 80 degrees sidewall angle in deep Si.

The Si_Slope recipe, recently developed at Tyndall on the STS-HRM, provides about 80 degrees sidewall angle in deep Si.

Contact : John Barton : john.barton@tyndall.ie | webpage

Relevant Projects : MNT Europe