NMRC: Research Highlights - Microelectronics

NMRC is involved in all aspects of microelectronics research and development from the development of novel materials and processes to the interconnection and packaging of advanced microelectronic devices for industry.

There are many examples of the microelectronics technologies under development in NMRC and the following highlights have been selected to demonstrate the diversity and quality of the work.

MICROELECTRONICS TECHNOLOGY DEVELOPMENT

• Thin Dielectric Processing
  During 1999, a high value integrated capacitor structure to be utilised in a range of applications in digital and analogue applications has been developed. The capacitor was formed using a planar polysilicon/insulator/polysilicon approach and a cross sectional transmission electron micro-graph of the structure is shown in Figure 1 below. For the thin dielectric region both oxide-nitride-oxide (ONO) and nitrided SiO2 were investigated. The thin dielectric regions were formed using rapid thermal processing, and dielectric layers of 30Å and below were formed on the first polysilicon layer, resulting in a specific capacitance per unit area in excess of 11fF/micron2. Full integration of the capacitor structure into a 3-level metal BiCMOS process was achieved.
  
  STEM cross section of a high value double polysilicon capacitor.
• Non-Volatile Memory
  
  Figure 2:- Trade-off between leakage current and read current as a function of the gate length and read current in a flash EEPROM. Enlarge

  Process and device simulation has been used to help develop and optimise embedded flash EEPROM in a 0.18 micron CMOS technology in collaboration with Philips Research. The results in Figure 2 illustrate the trade-off between leakage current and read current as the gate length and read current are varied. Through simulation, the optimum device gate length and read voltage were determined. The targets for high read current and low leakage current were achieved at a read voltage of 0.5V and gate length of 0.3micron. The symbols show the measured results fabricated after the simulation study and the close agreement validates this methodology.

• Development of a Silicon Microswitch

  Figure 3:- Development of Silicon Microswitch.

  Micro-electro-mechanical systems (MEMS) are based on the 3-dimensional processing of silicon to provide non-electronic functions or components. NMRC has produced its first proof-of-concept prototypes of electrostatically activated micro-switches using surface micromaching of silicon. One of the key novelties of the fabrication process is that it is CMOS-compatible, which will allow the development of a smart switch component with the CMOS circuitry providing the intelligence (see Figure 3).

  Furthermore, the switch process can be introduced to existing CMOS production processes, which will be a major benefit to its future commercialisation.

• Thin Film Magnetics on Silicon
  The integration of magnetic components onto silicon substrates using electroplated copper combined with BCB dielectric photoprocessing has been investigated (see Figure 4 below). This technology has the potential to allow the integration of transformers, inductors and micro-relays on-chip, essentially as a post process to standard IC fabrication processing. Application areas of interest for this technology include isolated signal transmission in data-communications and micro-power conversion for portable electronic equipment where micro-power converters may be used to supply voltages other than the battery voltage.

  Figure 4:- Thin film magnetic structure on silicon showing plated copper windings on insulated permalloy.

MICROELECTRONICS MODELLING

• Compact Device Modelling
  As MOS devices are scaled into the sub-100 nanometre regime gate oxide thickness must be correspondingly reduced. Typical oxide thicknesses reported for 90 nanometre gate length devices are in the region of 1.5 nanometre. As the thickness of the gate dielectric is decreased, gate current, due to direct tunnelling of carriers across the gate dielectric, becomes a feature of device operation. During the year, a macro-model for the simulation of devices, with gate current due to direct tunnelling, was used to study the operation of MOSFETs in the presence of gate current. Compact model equations were formulated to relate the gate current to the drain and gate bias and also to divide the gate current between the source and drain terminals of the device. Figure 5 shows the fit to the measured gate current of a MOSFET with a 2.5 nanometre gate oxide using the new model.

  Figure 5:- Fit to measured gate current of MOSFET with 2.5nm gate oxide using newly developed compact model.

• Computational Modelling
  NMRC is applying computational materials science studies to the problem of device reliability for GaAs based, high-frequency bipolar transistors. Doping of these devices is achieved by incorporating carbon during epitaxial growth of the device layers. Hydrogen is present during the epitaxial growth steps and can attach itself to the carbon dopant atoms, thereby passivating it. During the project, a defect containing two carbon atoms (grey spheres) and a single hydrogen atom (white sphere) has been identified in the GaAs materials. The electronic structure of the defect and its impact on device operation and reliability is being calculated at NMRC and correlated to optical and electrical measurements.
• Thermal Modelling
  3-dimensional computational fluid dynamic (CFD) techniques were used to characterise the thermal performance of microwave and power modules (see Figure 6).

  Figure 6:- CFD modelling of power modules.