The group’s contribution to the development of 3D stacked circuits for future Complementary Metal Oxide Semiconductor (CMOS) technology is based on novel high mobility III-V channel materials. This 3D technology objective is aimed at providing a new paradigm shift in density scaling combined with a dramatic increase in the power efficiency of CMOS circuits. Our approach is based on the use of high mobility channel materials, such as InGaAs, utilized for n channel MOSFETs at low processing temperatures (<600ºC) for 3D transistor stacking.
One intermediate objective of the group, in partnership with European collaborators, is to validate InGaAs layer transfer for implementation on 300mm silicon wafer technology, followed by benchmarking InGaAs n-type FETs with relevant contact dimensions against planar and non-planar Si based solutions at the 14nm node and beyond.
The present objective of this activity based on the ITRS roadmap is to integrate – on 300mm silicon wafers – monolithic 3D CMOS circuits with 14nm node gates based on n-type InGaAs transistor devices on top of p-type (Si)Ge transistor devices which are independently optimized.
The group are investigating III-V materials such as InGaAs, GaSb and InGaSb for III-V semiconductor solutions for both n-type and p-type nanowire transistors that will be suitable for the co-integration of RF technology with digital CMOS on 300mm silicon wafers.
The development of p-type III-V MOSFETs are far behind the equivalent n-type transistors, so there is particular focus on finding a replacement to Si and (Si)Ge p-type transistor technology. The advantageous transport properties of III-V materials include a high injection-velocity, a high mobility, and combined with reduced scattering strength, this enables increased drive currents at reduced drive voltages.
Development and optimization of III-V nanowire MOSFETs in particular would be highly advantageous for future technology nodes given their improved electrostatic control to reduce short channel effects, flexible heterostructure design to increase the transistor breakdown voltage, reduced scattering strength to promote ballistic transport and circuit linearity, and reduced defect contribution for III-V integration on 300mm Si substrate technology.
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