Design robustness to minimise the risk of IC damage due to Electro Static Discharge (ESD) continues to challenge the semiconductor industry. Computer modelling of ESD protection is key and the Transmission Line Pulse (TLP) methodology takes centre stage as the technique for acquiring the necessary data. The Design Technology Evaluation Group (DTE) has a constant impedance TLP measurements system and performs ESD characterisation measurements for industry under contract.
TLP testing involves the application of a short duration (0.2ns rise time) rectangular current pulse to the structure being measured. The resultant voltage is measured. For IC design analysis of ESD performance, TLP measurement has replaced HBM testing. TLP measurements may also be calibrated for a specific process against HBM ESD measurements. Early failure is better understood using the in-situ leakage measurement capability of the TLP system.
Key is selection of the correct rise time and pulse width to deliver the same energy as the Human Body Model (HBM) pulse of the same peak energy. TLP measurements accurately replicate the HBM. The typical test conditions are = 200V, 3A, 100ns Pulse Width and 600ps Rise Time. Our system performance is: V max = 1200Volts. I max = 21Amps. VF Pulse widths from 5, 10, 15, 20ns. Pulse rise times 600ps,2,5,10ns. The system has both DC and Pulsed characteristic curve capability, as well as 3 biasing voltage supplies.
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