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Leader in Integrated ICT Hardware & Systems

Circuits & Systems

 

The Circuits and Systems Group specialises in the modeling, simulation, analysis and design of nonlinear mixed-signal circuits and systems for applications in communications and signal processing.  The group has particular expertise in techniques such as nonlinear dynamical system theory and mixed-signal simulation; it targets applications including oscillators, digital delta-sigma modulators (DDSM) and fractional-N frequency synthesizers.

The theoretical and solution-focused research bridges the traditionally separate fields of Circuits and Systems and Solid-State Circuits.  We publish primarily at the International Symposium on Circuits and Systems and in the IEEE Transactions on Circuits and Systems, as well as the European Solid-State Circuits Conference and in the Journal of Solid-State Circuits.  We have also published monographs on DDSMs and All-Digital Phase-Locked Loops.

Our recent theoretical innovations include injection-locked frequency dividers, error masking, and bus-splitting, which have enabled high-speed and reduced-complexity DDSMs.  Our patented DDSM technology underpins the best-in-class performance of a commercial family of monolithic fractional-N frequency synthesizers.

Current research is focused on minimising nonlinearity-induced spurs and noise in high-performance frequency synthesizers for wireless and wireline applications.  In addition, we are investigating novel synthesizer architectures for low-energy edge-of-network nodes in the Internet of Everything.
 

Partners:

  • Analog Devices
  • Politecnico di Milano
  • Seconda Università degli Studi di Napoli
  • Università degli Studi di Pavia
  • Università degli Studi di Napoli Federico II

Funders:

  • Analog Devices
  • Irish Research Council
  • Science Foundation Ireland
Circuits & Systems
Simulated power spectral density of the output of a nested bus-splitting 1-2-3 DDSM with a 16-bit sinewave input at 20 kHz, a bandwidth of 20 kHz, and an oversampling rate of 128. The solid curves show the zeroth-order quantization noise associated with the sinusoidal input (green) and the first-, second-, and third-order shaped quantization noise contributions (red) of the corresponding DDSMs.  The first- and second-order contributions are spectrally masked by the third-order shaped quantization noise.  This reduced complexity architecture occupies 62% of the area and consumes 51% of the power of its conventional counterpart. 
Circuits & Systems
Measured spectrum of nominally 4.0 GHz frequency synthesizer output without (yellow) and with (cyan) nested bus-splitting DDSM technology.  In the former case, there is a frequency error of approximately 2.44 Hz; in the latter, there is no frequency error

 

 

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